The present invention relates to a process and a device designed to perform the process for outputting a digital signal, in particular in a digital signal transmission according to LVDS transmission standard in which a differential signal of low voltage and limited current is used.
Applicants claim priority to German Application No. 102 55 642.3, filed Nov. 28, 2002, the entire application of which is incorporated by reference.
U.S. Pat. No. 6,288,581 B1 discloses an LVDS output driver in which the positive and the negative signals of the differential output signal are each generated by a main complementary end stage, wherein the two main complementary end stages are connected in parallel and triggered in counter-phase. Allocated to each of the two main complementary end stages is an auxiliary complementary end stage, the output of which can be connected with the output of the allocated main complementary end stage and controlled in synchrony with the allocated main complementary end stage. At each edge of the control signals to trigger the main complementary end stages, for short periods the outputs of the auxiliary complementary end stages are connected with those of the main complementary end stages to increase briefly the output current after a signal change and thus improve the edge steepness. In each case, the two main complementary end stages and the two auxiliary complementary end stages are connected in parallel and together receive a constant current to limit the output current to a current limit value. Disadvantageously, this output driver requires a high circuit complexity as the driver circuit must be provided in duplicate and in addition the connection elements with the necessary control logic are required for connecting the outputs of the auxiliary complementary end stages and the main complementary end stages.
Furthermore, U.S. Pat. No. 6,281,715 B1 discloses an LVDS driver in which a positive and a negative output of a differential output signal are each generated by a complementary end stage, the two complementary end stages being controlled in counter-phase, connected in parallel and exposed jointly to a constant current in order to limit the current of the differential output signal. The constant current for application to the parallel circuit of the two complementary end stages can be briefly increased by means of additional current switching elements on each edge of the trigger signal of the two complementary end stages. Disadvantageously, this requires an increased circuit complexity for the additional current switching elements, an equally necessary additional current source and a device for temporally correct triggering of the circuit switching elements to supply the additional current.